1.Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing a complementary metal-oxide-semiconductor (CMOS).
2.Description of Related Art
Metal-oxide-semiconductor (MOS) transistors are now one of the most widely used type of semiconductor devices in VLSI circuits. MOS devices can be further classified into n-channel MOS or NMOS, p-channel MOS or PMOS and complementary MOS (CMOS), wherein NMOS is still the most frequently used device type. However, as the level of integration for semiconductor devices continues to increase, NMOS devices are gradually being replaced by CMOS devices. This is because a CMOS device consumes less power and hence generates less heat than an NMOS device. Low power consumption and low heat generation make a CMOS device more stable and more reliable.
FIGS. 1A through 1F are cross-sectional views showing the progression of manufacturing steps in producing a conventional P-well CMOS. First, as shown in FIG. 1A, a p-well 102 is formed in an n-type substrate 100. Thereafter, a field oxide region 104 is formed over the substrate 100. The field oxide region 104 is used to separate the portion of the p-well where an NMOS transistor is to be formed from the portion of the n-type substrate 100 where a PMOS transistor is to be formed.
In the subsequent step, an NMOS transistor gate 106 and a PMOS transistor gate 108 are formed above the p-well 102 and the silicon substrate 100, respectively. Then, a photoresist layer 110 is deposited over the portion of the n-type substrate where the PMOS is to be formed, the field oxide region 104 and the region in the p-well where a well pickup structure 111 is to be formed. Next, a low-concentration n-type impurity implantation 112 is carried out using the photoresist layer 110 and the gate 106 as masks. Hence, lightly doped NMOS source/drain regions 114 and 116 are formed.
Next, as shown in FIG. 1B, again using the photoresist layer 110 and the gate 106 as masks, a low-concentration p-type impurity implantation 118 is carried out at a tilt angle .theta.. Ultimately, a halo region 120 is formed underneath the NMOS source/drain regions 114 and 116. The halo region 120 is capable of reducing device punch-through.
Next, as shown in FIG. 1C, the photoresist layer 110 is removed, and then sidewall spacers 122 and 124 are formed on the sidewalls of the gates 106 and 108.
Next, as shown in FIG. 1D, another photoresist layer 126 is formed over the substrate 100. This photoresist layer 126 covers the portion of the n-type substrate 100 were the PMOS is to be formed, the field oxide region 104 and the portion of the p-well 102 where the well pickup structure 111 is to be formed. Subsequently, using the photoresist layer 126, the gate 106 and sidewall spacers 122 as masks, a high-concentration n-type impurity implantation 128 is carried out. Ultimately, heavily doped NMOS source/drain regions 130 are formed.
Thereafter, as shown in FIG. 1E, the photoresist layer 126 is removed, and then another photoresist layer 132 is deposited over the substrate 100. The photoresist layer 132 exposes portion of the substrate 100 where the PMOS is to be formed and portion of the p-well 102 where the well pickup structure 111 is to be formed. Subsequently, using the photoresist layer 132, the gate 108 and the sidewall spacers 124 as masks, a high-concentration p-type impurity implantation 134 is carried out. Therefore, heavily doped PMOS source/drain regions 138 are formed in the n-type substrate 100, and at the same time well pickup region 136 is formed in the p-well 102.
Finally, as shown in FIG. 1F, the photoresist layer 132 is removed to complete the CMOS fabrication.
As the level of integration for CMOS devices increases, the aforementioned method of fabricating the p-well of a CMOS encounters some problems. One such problem arises when the halo implantation 118 is carried out. Since the photoresist layer 110 has a thickness 140 of more than about 13000 .ANG. and the distance 142 between the gate 106 and the photoresist layer 110 is only about 4000 .ANG. due to the need to cover the well pickup region, maximum tilt angle .theta. for carrying out ion implantation must be reduced from about 30.degree. to 15.degree. or lower. In the worse case, when factors such as alignment errors result from alignment accuracy and critical dimensions of the device, the restrictions may be so severe that it is impossible to form the halo region 120. Hence, device punch-through can become a serious problem for the device.
In light of the foregoing, there is a need to provide an improved method of fabricating CMOS devices.